Method and apparatus for integrating and determining whether a memory subsystem is installed with standard page mode memory or an extended data out memory

ABSTRACT

In a memory subsystem having a plurality of memory banks populated with up to a corresponding plurality of dynamic random access memory (DRAM) modules, the DRAM modules being of an extended data out type DRAM module or a page mode type DRAM module, ascertaining the type of DRAM module installed in populated ones of the plurality of memory banks. The DRAM type is determined by storing a predetermined value to a predetermined location in populated ones of the plurality of memory banks, and subsequently reading data from the predetermined location of populated ones of the plurality of memory banks using a page read control signal suitable for the extended data out type DRAM modules. If the data read corresponds to the predetermined value stored, an extended data out type DRAM module is identified.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to the field of computer systemmemory. More specifically, the present invention relates to an apparatusfor integrating standard page mode dynamic random access memory (DRAM)devices with extended data-out DRAMs and a method for distinguishingbetween the type of DRAM populated in a memory subsystem in a computersystem.

[0003] 2. Description of Related Art

[0004] Personal computer systems are becoming increasingly more powerfuland less expensive. At present, personal computer systems are achievingprocessing performance levels previously achieved only bymini-computers. And as the demand for high performance computerscontinues to grow, system designers will develop faster and morepowerful microprocessors.

[0005] As microprocessors become increasingly faster, the speed ofmemory devices continue to be a major limiting factor in determining theperformance of the computer systems. Specifically the memory speed canlimit how fast application programs will run. While fast memory devicessuch as static random access memory (SRAM) devices are available, theiruse in main memory in a computer system is not common due to therelatively high cost of these memory devices.

[0006] Most system designers use dynamic random access memory (DRAMs)devices in main memory due to their relatively low cost and low powerconsumption. However, the slower speed of DRAMs tend to impede theperformance of high performance microprocessor based computers.

[0007] To improve the performance of the DRAM devices, many systemdesigners use page mode DRAMs. In a paged memory device memory istypically accessed by the underlying processor of the computer system byissuing an address that selects a particular location in the memoryarray. The address is then loaded into a memory controller which handlesthe task of providing row and column addresses used by the DRAM from theaddress provided by the processor.

[0008] After receiving an address from the processor, the memorycontroller places the row and then the column address on the DRAM'saddress bus in response to the timing requirements of the DRAM. In priorart computer systems using standard page mode DRAMs, the microprocessorissues a full address to access a specific memory location via thememory controller. To handle address requests to main memory, prior artmemory controllers include latches to temporarily retain previousaddress requests from the processor which are then compared withincoming addresses to determine if the DRAM's row and column addresseshave changed between successive memory requests.

[0009] In addition to the memory controller retaining addresses, theDRAMs retain data which require periodic refreshes. Refreshing the DRAMdelays data fetches from a page in the DRAM due to the reasserting ofcontrol signals to the DRAM to reinitiate memory accesses in progressprior to a refresh cycle. Specifically, the row address strobe signal(RAS#) to the DRAM must be reasserted to reopen the page being accessedprior to the refresh. In reopening the page, the falling edge of thecolumn address strobe (CAS#) is used to strobe a column address in theDRAM. Strobing the column address requires that CAS# be deasserted for aperiod typically referred to as precharge period. There is a minimumtime between precharge and the next data being made available by theDRAM. The DRAM turns off its output signals when the CAS# is highrequiring that the CAS# stays low until data is captured by the memorycontroller thereby delaying the precharge and subsequent availability ofthe next piece of data from the DRAM. This causes delays that cause waitstates in a read cycle and thus slow down the performance of theunderlying processor.

[0010] To alleviate the delays caused in accessing data due to the CAS#precharge time, system designers use a fast performance DRAM deviceknown as the Extended Data Out DRAM (EDO DRAM) which have the samepackaging and power characteristics as the page mode DRAMs and do nottristate the data output when CAS is deasserted, but have differenttiming requirements than the standard page mode DRAMs and do not causethe delays after a refresh cycle that are characteristic of the standardpage mode DRAMS.

[0011] Although various types and sizes of the DRAMs (e.g., EDO DRAMsand the standard page mode DRAMs) may be installed in the memorysubsystem in the computer, the computer must be configured properly inorder to access the different types of DRAMs. In some prior art systems,the computer system is configured by use of hardware switches forspecifying a plurality of memory configuration parameters. Theseparameters include the presence of a memory device in a particular bank,the type of memory device, and the size of the memory device. The use ofhardware switches however requires the user to be knowledgeable of thevarious memory devices installed in the computer system.

[0012] Furthermore, despite performance advantage that the EDO DRAMshave over the current standard page mode DRAMs, system designers havenot found a way to effectively integrate the EDO DRAMs into existingcomputer systems. Current implementations use either the standard pagemode DRAMs or the EDO DRAMs. So, for example, if a computer user, whodoes not know much about the differences between memory devices,purchases a system designed to use the EDO DRAMs, the user may not beable to add a standard page mode DRAM purchased from the local computerstore into the computer and derive the same performance if the computerhad either all standard page mode DRAMs or EDO DRAMs. Mixing the twoDRAM types slows performance because if the computer system is designedto take only standard page mode DRAMs, adding EDO DRAMs results in theEDO DRAMs using page mode DRAM timings or not working at all. On theother hand, if the computer user adds standard page mode DRAMs to asystem designed for EDO DRAMs, the system will perform slowly becausethe memory controller is not able to distinguish between the EDO DRAMand the standard page mode DRAM due to the differences in the controland timing requirements of the two types of memory.

[0013] Thus, a system that effectively integrates and automaticallyconfigures various types of DRAM memory devices installed in the memorysubsystem is needed.

SUMMARY OF THE INVENTION

[0014] The present invention provides a method and apparatus forintegrating and distinguishing between memory banks populated with astandard page mode dynamic random access memory device (DRAM) or anextended data-out (EDO) DRAM in a memory subsystem. The preferredembodiment includes a plurality of configuration registers—each a bitwide—having stored information that identifies the type of DRAM deviceinstalled in a memory bank. Particularly, each configuration registercorresponds to one or more rows of memory banks of DRAMs installed inthe memory subsystem.

[0015] The preferred embodiment includes a DRAM bank decoder havingdecoding logic for decoding bank locations responsive to addressrequests from the processor in the computer system to the memorysubsystem. The preferred embodiment further includes a detection logiccircuit for detecting bits specified by the configuration registerscorresponding to each memory bank populated with a DRAM device. Thedetection logic in combination with the decode logic determines whethermemory bank locations in the memory subsystem is populated or not.

[0016] Memory access control signals comprising a row address strobe(RAS), a column address strobe (CAS), and an address strobe (ADS) areutilized by the preferred embodiment for control and timing requirementsof the DRAM devices installed in the memory subsystem. A CAS statemachine controls the various states of accesses to the DRAM devices. TheCAS state machine in combination with the detection logic determineswhether an address received by the memory subsystem is designated to thestandard page mode DRAM or the EDO DRAM.

[0017] Advantages of the preferred embodiment of the present inventioninclude the effective integration of various types of DRAM memorydevices with different control and timing requirements in the samememory subsystem without degrading performance. The preferred embodimentalso has the advantage of automatically storing information foridentifying the type of memory device installed in a memory bank tospare the system user the inconvenience of determining the memory typeand then manually setting hardware switches to configure memory.

[0018] The CAS state machine of the preferred embodiment allows memoryaccess requests to either the standard page mode DRAM or the EDO DRAMwithout inserting an inordinate amount of wait states to slow the systemdown.

[0019] The features and advantages described in the specification arenot all inclusive, and particularly, many additional features andadvantages will be apparent to one of ordinary skill in the art in viewof the drawings, specification and claims hereof. Moreover, it should benoted that the language used in the specification has been principallyselected for readability and instructional purpose, and therefore resortto the claims is necessary to determine the inventive subject matter.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020]FIG. 1 is a block diagram illustration of a typical architectureof a computer system of the present invention.

[0021]FIG. 2 is a block diagram illustrating a processor, a memorycontroller, and memory including both a standard page mode dynamicrandom access memory (DRAM) device and extended data-out DRAMs.

[0022]FIG. 3 is a block diagram of the memory controller including theconfiguration registers, the bank decoder, the Column address strobe(CAS) and Row address strobe (RAS) state machines, and detection logiccircuit.

[0023]FIG. 4 is a timing diagram of the CAS state machine illustratingthe various states of the CAS signal during an address request to thestandard page mode DRAM and the EDO DRAM.

[0024]FIG. 5 is a flow chart illustrating the method of distinguishingpopulated memory banks populated with either the standard page modeDRAMs and the EDO DRAMs.

[0025]FIG. 6 is a waveform diagram of a read cycle of the EDO DRAMdevice.

[0026]FIG. 7 is a waveform diagram of a read cycle of the standard pagemode DRAM device of the prior art.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0027]FIGS. 1 through 7 of the drawings disclose various embodiments ofthe present invention for purposes of illustration only. One skilled inthe art will readily recognize from the following discussion thatalternative embodiments of the structures and methods illustrated hereinmay be employed without departing from the principles of the invention.

[0028] Overview of the Computer System

[0029] Reference is first made to FIG. 1 which is a block diagramillustrating a computer system of the present invention. As illustratedin FIG. 1, a computer system 100 of the present invention generallycomprises a bus 101 for communicating information, a processor 102coupled to the bus 101 for processing instructions, a main memory 103coupled to the bus 101 for storing data and instructions for theprocessor 102, and a cache memory 104 also coupled to the bus 101 fortemporarily storing data and instructions for the processor 101. Amemory controller 105 is also shown coupled to the bus 101 forcontrolling access to the main memory and a cache memory 104.

[0030] The computer system 100 also includes a display device 110coupled to the bus 101 for displaying information to the computer user,an alphanumeric input device 112 coupled to the bus 101 forcommunication information and command selections to the processor 102,and a storage device 114 also coupled to the bus 101 for storing datafor the computer system 100.

[0031] Reference is now made to FIG. 2, which is a block diagramillustrating one embodiment of the preferred embodiment of the presentinvention. As illustrated in FIG. 2, the processor 102 is coupled to themain memory 103 via the address bus 200 to send address requests to themain memory 103. The processor 102 is also coupled to the memorycontroller 105 via the Address Strobe (ADS#) signal 210. The processor102 initiates a read or write cycle to the memory subsystem by assertingthe ADS# signal 210 to the memory controller 105.

[0032] The memory controller 105 is coupled to the main memory 103,which comprises a standard page mode DRAM device 225 and an ExtendedData Out DRAM (EDO) device 230, via the Row Address Strobe (RAS#) signal215 and the Column Address Strobe (CAS#) signal 220. The ADS# 210, theRAS# 215, and the CAS# 220 signals are labeled with a “#” to indicatethat the signals are low when asserted (i.e., active low).

[0033] In a normal mode of operation, the processor 102 applies anaddress and control signals to address bus 200 and asserts the ADS#signal 210 to the memory controller 105. The memory controller 105receives the address and control signals from the bus 100. Depending onthe specified address and control signals, the memory controller 105signals to the main memory 103 via the CAS# 220 and RAS# 215 signals. Onreceipt of the memory access control signals from the memory controller105, data is transferred via the data bus into either the EDO 230 orstandard page mode DRAM 225 for a write operation, or data istransferred from either of the DRAMs to the processor 102 for a readoperation.

[0034] Reference is now made to FIG. 3, which is a block diagramillustrating the internal architecture of one embodiment of the memorycontroller 105 of the preferred embodiment. Some of the components andthe operation of the memory controller 105 is well known in the art andwill not be described in detail. However, the memory controller of thepreferred embodiment includes a plurality of configuration registers 300each of the configuration storing information identifying the DRAMdevice stored in a memory bank, a DRAM bank decoder 310 includingdecoding logic for decoding address requests to the various memory banklocations, and a multiple input select multiplexer 320 includingdetection logic circuitry for detecting which memory banks are populatedwith the DRAM devices. The memory controller 105 also includes a columnaddress strobe state machine 330 and a row column address strobe statemachine 340. The function of the RAS state machine is well known in theart and will not be described in detail.

[0035] Still referring to FIG. 3, the memory configuration registers 300store information related to memory devices installed in the main memory103. In the preferred embodiment, the number of registers corresponds tothe number of memory banks in the main memory 103. Configurationinformation is loaded into each of the registers during theinitialization of the computer system and any subsequent addition of aDRAM device to the computer system after initialization. The memorycontroller 105 of the preferred embodiment also includes a detectionlogic to determine memory pull-ups or pull-downs depending on theconfiguration information presented by the system BIOS.

[0036] The address bank decoder 310 including decoding logic decodes theDRAM bank location in the main memory 103 in response to an addresspresented by the processor 102. The bank decoder 310 is coupled to aSelect multiplexer 320 and a RAS# state machine 330 via DRAM bank lines315. The Select multiplexer 320 includes the detection logic which incombination with the decoding logic selects which memory bank a memoryaccess request—specifically a read request—is destined. The Selectmultiplexer 310 is coupled to a CAS# state machine 330 via a selectsignal 325. The memory controller 105 also includes a RAS# state machine340 which is coupled to the DRAM bank decoder 310 and the Selectmultiplexer 320 via a decode lines 335. The address bank decoder 320also couples to the ADS# signal 215 from the processor 102.

[0037] During a normal system boot operation of the preferred, thesystem BIOS (not shown) configures boot registers to configure thevarious memory banks in the system. The system BIOS then presents thisinformation to the configuration registers 300 to be stored so that thememory controller knows the contents of each bank of memory in thesystem (i.e., whether a bank contains EDO or standard DRAM). In thememory controller of the preferred embodiment, each of the configurationregisters is a bit wide and is set by the memory controller 105 when acorresponding memory bank containing the DRAM devices is being accessed.During a read operation to the main memory 103, the memory controller105 presents the configuration information to the select multiplexer 320so that access requests to a specific memory bank is decoded and theappropriate DRAM device is selected. After selecting the appropriateDRAM device based on the decode and the configuration information, theselect multiplexer 320 signals the CAS state machine 330 which thencontrols the timing requirements of the particular DRAM device beingaccessed. The operation of the CAS state machine is described in detailin FIG. 4. Although the configuration registers 300 and the CAS statemachine 330 as described are embodied in the memory controller of thepreferred embodiment, the configuration registers 300 and the CAS statemachine 330 may be embodied in other components of the computer system100.

[0038] Referring now to FIG. 4 is a block diagram illustrating oneembodiment of the CAS# state machine 330 of the memory controller of thepreferred embodiment. The DRAM memory array of the preferred embodimentis organized as a number of banks. Each bank has up to one or more rowsand a certain number of banks may be populated at any one time dependingon how the memory array is configured.

[0039] Each row is also organized into a number of pages such that anytime an access is made in the main memory 103, that location resides ina certain page of the rows. In the page mode operation as describedearlier, significant performance can be gained if successive accesses tomemory are written to the same page.

[0040] As illustrated in FIG. 4, the CAS state machine 330 controls thevarying timing requirements of the DRAM devices so that memory access tothe EDO DRAMs is not handled the same way as an access to the page modeDRAM. As illustrated, at state 0, the CAS# state machine 330 is idlewhen a cycle (write or read) is not being driven on the address bus bythe processor 102. The CAS# signal is not asserted at this state. Oncethe CAS# is asserted by the memory controller 105 indicating a requestto the main memory 105, the CAS# state machine transitions to state S1when data needs to be read from an EDO DRAM bank. After a requestedaddress has been read from the requested EDO DRAM bank location, theCAS# state machine transitions to state S3 for a precharge of the CAS#inputs for each piece of data read after the first in a burst read, thestate machine transitions back to state S0 after the last piece of datais read. If, on the other hand, there is more data to be read, the statemachine transitions back to state S1 for a reasserting of the CAS#signal to perform another access to the EDO DRAM bank locations afterthe precharging of the CAS# signal.

[0041] During a read cycle to the page mode DRAM devices, the processor102 initiates an access request to the DRAM banks in the main memory 103at state S0, upon receipt of the request, the memory controller 105asserts the CAS# signal at state S1. After the access to the page modeDRAM banks is completed, the state machine transitions into a wait statewhich lasts for one or more clocks at state S2. After the wait period isover, the state transitions to state S3 for a precharge of the CAS#inputs. After a piece of data has been read, the state machinetransitions back to state S0, otherwise; the state machine transitionsto state S1 where the CAS# signal is reasserted by the memory controller105 for another access of the main memory 103.

[0042] Reference is made to FIG. 5, which is a flow chart illustratingthe detection logic of one embodiment of the preferred embodiment of thepresent invention for distinguishing between main memory banks populatedwith the page mode DRAMs and those populated with EDO DRAMs. Asillustrated at box 500, the DRAM bank detection of the preferredembodiment begins with the system BIOS configuring the configurationregisters in the memory controller with main memory bank informationspecifying which banks in main memory are populated with the DRAMs.

[0043] In box 510, after the sizing of the main memory banks, thedetection logic configures the configuration registers to store a binaryvalue of “1s” in each memory bank found populated with the DRAMs. Atthis stage of the boot up process, the memory controller assumes themain memory banks are populated with only standard page mode DRAMs.After configuring the configuration registers, processing continues atbox 520.

[0044] At box 520, the detection logic programs the memory controllerfor EDO detect mode enabling the memory controller to distinguishbetween the memory banks containing EDO DRAMs and those containingstandard page mode DRAMs. After programming the memory controller forEDO DRAM detection, processing continues at box 530.

[0045] At box 530, during a memory access to main memory 103, the memorycontroller 105 sets the first DRAM bank found at box 500 to be thecurrent bank being accessed. After setting the first DRAM bankencountered, the memory controller 105 reads the location of the currentDRAM bank and checks the corresponding configuration register todetermine if the register contains “1s” at box 540.

[0046] If the configuration register contains “1s” based on the check atbox 540, the memory controller 105 programs the current bank to be anEDO bank; otherwise, the current bank is programmed to be a page modebank. After the memory controller 105 has been programmed to detect allthe DRAM banks populated in main memory, processing continues atdecision box 550.

[0047] At box 550, a determination is made whether the current DRAM bankis the last DRAM bank populated in the main memory 103. If the currentbank is the last bank installed with the DRAM devices, the detection andconfiguration processes ends at box 585; otherwise processing continuesat box 590 where the next bank being checked is set to be the currentbank.

[0048] Referring now to FIG. 6 is a timing diagram illustrating a readcycle operation to the extended data-out DRAM device of the preferredembodiment. As illustrated in FIG. 6, a read operation to the EDO DRAMcomprises three steps and begins at step 1 when the first column address610 is driven by the memory controller 105 at the clock 1. The addresshas a minimum setup to the falling edge of the CAS# signal 220.

[0049] At step 2, the CAS# signal 220 is driven low by the memorycontroller 105 at the clock 2. At clock 2, the EDO DRAM has a minimumdata access time from the falling edge of the CAS# signal 220.

[0050] At step 3, the CAS# signal 220 is driven high by the memorycontroller 105. The EDO DRAM unlike the standard page mode DRAMscontinues to drive data even though the CAS# signal 220 is driven highto make data 620 available at clock 3. Steps 1,2, and 3 are repeated foreach piece of data read from the DRAM.

[0051]FIG. 7 is a timing diagram illustrating a read operation to astandard page mode DRAM of the prior art. As illustrated in FIG. 7, aread operation comprises four steps and begins at step 1 when the memorycontroller 105 drives the first column of an address 710 at clock 1.

[0052] At step 2, the CAS# signal 220 is driven low by the controller105 at clock 2. The standard page mode DRAMs, like the EDO DRAMS, have aminimum data access time from the falling edge of the CAS# signal 220until the rising edge.

[0053] At step 3, the CAS# signal 220 continues to remain low at clock3. The standard page mode DRAMs samples data at clock 4. Sampling dataat clock 4 requires the standard page mode DRAMs to tristate the databus requiring the memory controller 105 to keep the CAS# signal 220 lowfor an additional clock.

[0054] At step 4, the memory controller 105 drives the CAS# signal 220high at clock 4. The standard page mode DRAM has a minimum data accesstime from the falling and the rising edge of the CAS# signal 220. Steps1 through 4 are repeated for each piece of data read out of the pagemode DRAM.

[0055] As illustrated by the timing diagrams in FIGS. 6 and 7, a readcycle operation to the page mode requires an additional clock than aread cycle to the EDO DRAMs. The additional clock of CAS# assertionrequired to sample data in a page mode DRAM causes read operations tothe page mode DRAMs to be slower than read cycles to the EDO DRAMs.However, by effectively integrating the EDO DRAMs and the page modeDRAMs the preferred embodiment reduces the performance degradation ofthe prior art system and makes such degradation less obvious to theuser.

[0056] Thus, a method and apparatus for integrating and determiningwhether a memory subsystem is populated with a standard page mode DRAMdevice and an extended data-out DRAM device is described. From the abovedescription, it will be apparent that the invention disclosed hereinprovides a novel and advantageous method and apparatus fordistinguishing between the types of dynamic random access memory in acomputer system. The foregoing discussion discloses and describesexemplary methods and embodiments of the present invention. As will beunderstood by those familiar with the art, the invention may be embodiedin other specific forms without departing from its spirit or essentialcharacteristics, and thus, the described embodiment is not restrictiveof the scope of the invention. The following claims are indicative ofthe scope of the invention. All variations which come within the meaningand range of equivalency of the claims are to be embraced within theirscope.

What is claimed is:
 1. In a computer system having a memory systemhaving a plurality of types of dynamic random access memory (DRAM)devices including a first and a second type of DRAM, an apparatus forintegrating and automatically distinguishing between said first andsecond type of DRAM installed in said memory system comprising: (a) areceiving circuit for receiving configuration information responsive tosaid first and said second type of DRAMs; (b) a configuration circuitcoupled to said receiving circuit for configuring and storing saidinformation responsive to a plurality of memory locations installed withsaid first and said second types of DRAMs; (c) a determining circuitcoupled to said configuration circuit for determining which of saidmemory locations is installed with said first and said second types ofDRAMs; and (d) a timing controller circuit coupled to said determiningcircuit for controlling various states of an access request to each ofsaid first and second types of DRAM devices.
 2. The apparatus of claim 1further including a bank decoding circuit for decoding said memorylocations in said memory system in response to access requests to saidfirst and second type of DRAM devices, wherein each of said memorylocations is decoded as containing either said first type or said secondtype of DRAM.
 3. The apparatus of claim 1 further comprising a selectioncircuit for selecting a specific memory location containing said DRAMdevices in response to control signals issued from said configurationcircuit, said selection circuit coupled to said timing controllercircuit.
 4. The apparatus of claim 3, wherein said selection circuitincludes a plurality of inputs for receiving said control signals fromsaid configuration circuit and a single output for generating a selectsignal to said timing controller circuit.
 5. The apparatus of claim 1,wherein a separate circuit for storing configuration information isprovided for each of said memory banks.
 6. The apparatus of claim 1,wherein said DRAM devices includes a standard page mode DRAM and anextended data-out (EDO) DRAM.
 7. The apparatus of claim 1 wherein saidEDO DRAM retains and drives data out of its output during a precharge ofsaid EDO DRAM without imposing a wait state.
 8. The apparatus of claim 1wherein said standard page mode DRAM imposes a wait state during aprecharge of said DRAM.
 9. In a computer system having a memory systemincluding a plurality of dynamic random access memory (DRAM) devicesincluding a first and a second type of DRAM, a memory controller forintegrating and determining which type of said DRAMs is installed insaid memory system comprising: (a) a plurality of memory configurationregisters for storing information including bank contents of said memorysystem, said bank contents defining which of said banks is installedwith said first and second type of DRAMs; (b) a selector coupled to saidconfiguration registers for receiving said bank information from saidconfiguration registers, wherein said selector includes a single outputresponsive to either one of said first and second type of DRAM devices;(c) a detection logic circuit coupled to said selector fordistinguishing between access requests to either said first type or saidsecond type of DRAM; and (d) a timing controller for receiving anddisabling access control signals to each of said DRAM devices.
 10. Thememory controller of claim 9 including a DRAM bank decoder for decodingaccess requests received by said apparatus to a corresponding banklocation in said memory banks.
 11. The memory controller of claim 9wherein said timing controller is a column address strobe (CAS) statemachine.
 12. The memory controller of claim 9 wherein said DRAM bankconfiguration information is issued by a system BIOS of said computersystem.
 13. The memory controller of claim 9 wherein said timingcontroller issues a first signal to enable access said DRAM devices anda second signal to disable access to said DRAM devices.
 14. In acomputer system having a main memory system installed with a pluralityof types of dynamic access random memory (DRAM) devices including anextended data out (EDO) DRAM and a standard page mode DRAM, a method fordetermining which of said types of DRAM is installed in said main memorycomprising the steps of: (a) receiving configuration information foreach of said DRAM memory devices installed in said main memory; (b)configuring configuration registers for storing said configurationinformation so that each of said registers stores informationcorresponding to memory banks in said main memory; and (c) determiningwhich of said memory banks contains each of said DRAM devices inresponse to an access request to said main memory.
 15. The method ofclaim 14 further including the step of generating a bit identifier inresponse to said access requesting to a corresponding memory bankinstalled with either one of said DRAM devices.
 16. The method of claim14 further including the step of generating a select signal in responseto said bit identifier to a timing unit to meet timing requirements ofsaid DRAM device selected.
 17. The method of claim 14 wherein said step(c) includes the step of detecting a bit signal request from saidconfiguration register, and distinguishing which of said memory bankcorrespond to said bit signal.
 18. The method of claim 17 wherein saidstep (c) further includes the step of decoding said memory banklocations in said main memory in respond to said configurationinformation and said access request to said main memory.
 19. The methodof claim 14 further including the step of driving data out of said EDODRAM during a precharge step of said DRAM such that no wait states areimposed during a read operation to said EDO DRAM.